LeanVec reduces dimensionality for graph traversal, then reranks candidates using a full-dimensional but quantized secondary representation. The company says no float32 copy is retained when LeanVec is used.
The documented example uses the FAISS index name SVSVamana64,LeanVec4x8_128. Search tuning uses search_window_size, with search_buffer_capacity required to be at least as large. SVS is not enabled in default Milvus images: users must build Milvus from source with USE_SVS=ON. LeanVec and LVQ compression require Intel CPUs; the post recommends AVX-512 and says it used Xeon 6 hardware. Non-Intel deployments can use SVS FP32, FP16, or SQ8 storage modes.
Milvus benchmarked LeanVec4x8 against HNSW FP16 and SQ8 on four datasets, from 500,000 to 5 million vectors, using Milvus 3.0 pre-release code and 100 client threads. At roughly 95% recall on its tests, it reports 1.40x to 1.84x higher QPS than HNSW SQ8 and 24% to 38% lower P99 latency. The source does not establish equivalent results on other hardware, workloads, data distributions, or production Milvus releases.