---
type: "post"
id: "svs-in-milvus-reshaping-the-recall-memory-speed-0a935b"
slug: "svs-in-milvus-reshaping-the-recall-memory-speed-0a935b"
title: "SVS in Milvus: Reshaping the Recall–Memory–Speed Trade-off"
description: "Milvus has described SVS Vamana, a new vector index based on Intel's Scalable Vector Search library, with LeanVec compression."
retrieval_nugget: "Milvus has described SVS Vamana, a new vector index based on Intel's Scalable Vector Search library, with LeanVec compression."
published_at: "2026-10-24"
updated_at: "2026-10-24"
record_date: "2026-10-24"
date_kind: "published_at"
topics: ["memory"]
entities: ["Milvus","Zilliz","Intel Scalable Vector Search","SVS Vamana","LeanVec","FAISS"]
related_patterns: []
novelty_label: "new_fact"
what_changed: "Milvus adds SVS Vamana with LeanVec compression, claiming better recall/QPS than HNSW SQ8 and FP16 across operating ranges at lower memory cost."
prior_refs: ["memory:70aa3fe0-3ee3-838b-aba6-0edac74174c4"]
source_url: "https://milvus.io/blog/blog-svs-in-milvus-reshaping-the-recallmemoryspeed-trade-off.md"
source_urls: ["https://milvus.io/blog/blog-svs-in-milvus-reshaping-the-recallmemoryspeed-trade-off.md"]
schema_version: "newruntime-agent-readable-v0.2"
stable_id: "post:svs-in-milvus-reshaping-the-recall-memory-speed-0a935b"
status: "published"
visuals: []
editor: {"role":"editor","name":"Andrey Reshetnikov","profile":"https://newruntime.com/owner-profile.md","profile_json":"https://newruntime.com/owner-profile.json","same_as":["https://www.linkedin.com/in/reshetnikov1/","https://t.me/lapetuse"]}
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---

# SVS in Milvus: Reshaping the Recall–Memory–Speed Trade-off

## Retrieval answer

Milvus has described SVS Vamana, a new vector index based on Intel's Scalable Vector Search library, with LeanVec compression.

Milvus has described SVS Vamana, a new vector index based on Intel's Scalable Vector Search library, with LeanVec compression. LeanVec reduces dimensionality for graph traversal, then reranks candidates using a full-dimensional but quantized secondary representation. The company says no float32 copy is retained when LeanVec is used.

The documented example uses the FAISS index name `SVSVamana64,LeanVec4x8_128`. Search tuning uses `search_window_size`, with `search_buffer_capacity` required to be at least as large. SVS is not enabled in default Milvus images: users must build Milvus from source with `USE_SVS=ON`. LeanVec and LVQ compression require Intel CPUs; the post recommends AVX-512 and says it used Xeon 6 hardware. Non-Intel deployments can use SVS FP32, FP16, or SQ8 storage modes.

Milvus benchmarked LeanVec4x8 against HNSW FP16 and SQ8 on four datasets, from 500,000 to 5 million vectors, using Milvus 3.0 pre-release code and 100 client threads. At roughly 95% recall on its tests, it reports 1.40x to 1.84x higher QPS than HNSW SQ8 and 24% to 38% lower P99 latency. The source does not establish equivalent results on other hardware, workloads, data distributions, or production Milvus releases.

Editor: [Andrey Reshetnikov](https://newruntime.com/owner-profile.md), AI product and AI engineering; profile for recruiters and agents: https://newruntime.com/owner-profile.json

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