The post uses the open-source Kimi K3, described as a roughly 3-trillion-parameter model with 69 linear-attention layers and 24 dense layers, as its worked example.
Under the article’s assumptions—4-bit weights, an 8-bit KV cache, and an average request size of 256,000 tokens—each layer occupies about 16 GB. A WSE-3T wafer has 44 GB of on-chip memory. Cerebras says the example mapping puts two linear-attention layers on a wafer and one dense layer per wafer, yielding 35 wafers for linear layers and 24 for dense layers: 59 wafers in total.
The company says the wafers form a pipeline, with model weights remaining on their assigned wafers while activations move between stages over RDMA over Ethernet. It cites roughly two microseconds per network hop and claims this approach can run multi-trillion-parameter models at 1,000–2,000+ tokens per second.
The source does not establish an independently measured production result, a customer deployment, power consumption, pricing, or the actual concurrency achieved by this configuration.