---
type: "post"
id: "qwenputer-compiles-a-32-bit-risc-v-cpu-822444"
slug: "qwenputer-compiles-a-32-bit-risc-v-cpu-822444"
title: "Qwenputer compiles a 32-bit RISC-V CPU directly into Qwen3.5-4B's weights, no external runtime."
description: "Qwenputer is a project that says it implements a 32-bit RISC-V CPU directly in Qwen3.5-4B’s weights, without an external runtime."
retrieval_nugget: "Qwenputer is a project that says it implements a 32-bit RISC-V CPU directly in Qwen3.5-4B’s weights, without an external runtime. Its public checkpoint is 18.8 GB and is reported to run at about 3,200 CPU tokens per second on an L4, making it a systems experiment to inspect rather than a conventional execution platform to adopt."
published_at: "2026-11-02"
updated_at: "2026-11-07"
record_date: "2026-11-02"
date_kind: "published_at"
topics: ["models","open-source"]
entities: ["Qwenputer","Qwen3.5-4B","Hugging Face","RISC-V"]
related_patterns: []
novelty_label: "new_fact"
what_changed: "The Hugging Face release specifies a 32-bit RISC-V CPU compiled directly into Qwen3.5-4B’s weights, with no external runtime."
prior_refs: ["https://newruntime.com/posts/qwenpu-compiles-an-npu-into-qwen3-5-4b-077c19/"]
source_url: "https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer"
source_urls: ["https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer"]
schema_version: "newruntime-agent-readable-v0.2"
stable_id: "post:qwenputer-compiles-a-32-bit-risc-v-cpu-822444"
status: "published"
visuals: []
editor: {"role":"editor","name":"Andrey Reshetnikov","profile":"https://newruntime.com/owner-profile.md","profile_json":"https://newruntime.com/owner-profile.json","same_as":["https://www.linkedin.com/in/reshetnikov1/","https://t.me/lapetuse"]}
routes: {"html":"https://newruntime.com/posts/qwenputer-compiles-a-32-bit-risc-v-cpu-822444/","markdown":"https://newruntime.com/posts/qwenputer-compiles-a-32-bit-risc-v-cpu-822444.md","json":"https://newruntime.com/posts/qwenputer-compiles-a-32-bit-risc-v-cpu-822444.json"}
markdown_url: "https://newruntime.com/posts/qwenputer-compiles-a-32-bit-risc-v-cpu-822444.md"
---

# Qwenputer compiles a 32-bit RISC-V CPU directly into Qwen3.5-4B's weights, no external runtime.

## Retrieval answer

Qwenputer is a project that says it implements a 32-bit RISC-V CPU directly in Qwen3.5-4B’s weights, without an external runtime. Its public checkpoint is 18.8 GB and is reported to run at about 3,200 CPU tokens per second on an L4, making it a systems experiment to inspect rather than a conventional execution platform to adopt.

## Summary
Qwenputer is a project that says it implements a 32-bit RISC-V CPU directly in Qwen3.5-4B’s weights, without an external runtime. Its public checkpoint is 18.8 GB and is reported to run at about 3,200 CPU tokens per second on an L4, making it a systems experiment to inspect rather than a conventional execution platform to adopt.

## What happened
Qwenputer is presented on Hugging Face as a project built from Qwen3.5-4B. The project’s central claim is unusually specific: it compiles a 32-bit RISC-V CPU directly into the model’s weights and needs no external runtime. The wording matters. This is not merely a claim that a language model can describe RISC-V instructions or call a CPU simulator; the supplied material describes the weights themselves as containing the CPU implementation.

The project is publicly available as a Hugging Face checkpoint at https://huggingface.co/divagr1925/Qwen3.5-4B-Qwenputer. The accompanying discovery material says that its code has been open-sourced on GitHub at https://github.com/divagr18/qwenputer. That gives interested builders two public artifacts: a checkpoint to obtain and code to examine. The supplied material does not identify a commercial operator, hosted API, or managed service around either artifact.

The available numbers are limited but useful. The checkpoint is described as 18.8 GB. Performance is described as roughly 3,200 CPU tokens per second on an L4. The source does not define the benchmark workload behind that rate, specify a precision or batch configuration, or provide a baseline against a conventional RISC-V emulator. It also does not say whether the measurement reflects sustained execution, a particular program, or a broader suite of tests.

Several practical details are absent. The material does not state which RISC-V instruction subset is supported, whether memory behavior is implemented or tested, which programs can run, or how correctness was verified. It provides no release date, price, licence terms, deployment guide, access limits, or evidence of independent replication. “No external runtime” is the project’s stated property, but the supplied evidence does not define all the components excluded by that phrase.

The immediate significance is therefore bounded. Qwenputer is a published technical artifact making a strong architectural claim and supplying a size and one speed figure. It is not, on this evidence, a replacement for a normal processor, virtual machine, or emulator. Its value for a builder is as a concrete object through which to examine an unfamiliar proposition: that model weights can encode a processor-like computational structure.

## What the archive adds
This is a new fact in a known thread, not a restatement. [Nesformer](https://newruntime.com/posts/nesformer-compiles-an-nes-6502-cpu-ram-and-187393/) described an NES 6502 CPU, RAM, and cartridge ROM compiled into stock Qwen3.5. [QwenPU](https://newruntime.com/posts/qwenpu-compiles-an-npu-into-qwen3-5-4b-077c19/) described a vector unit compiled into Qwen3.5-4B weights and used to run the stories260K language model. Qwenputer contributes a separately identified 32-bit RISC-V CPU implementation.

## Trend signal
No supplied site pattern directly covers processor-like systems compiled into model weights; the strongest signal is the emerging archive thread rather than a confirmed broader operating pattern.

## Connections to other events
The archive now contains three distinct examples around Qwen3.5: an NES-oriented 6502 system, a vector-unit or NPU project, and Qwenputer’s RISC-V CPU claim. They should not be treated as equivalent products. They share a representation idea—structured computation encoded in a checkpoint—but the supplied material does not establish common methods, comparable performance, or interoperable execution environments.

## Why it matters
For teams building with AI, Qwenputer is a reminder to distinguish a model’s usual predictive role from the range of structures that may be represented in a model artifact. The experiment tests a boundary that conventional system design normally treats as fixed: software and execution machinery are separate from the learned weights being served. If that boundary is made porous, evaluation must cover more than output quality. Builders would need to inspect correctness, instruction coverage, reproducibility, resource use, and failure modes.

The reported constraints also matter. An 18.8 GB checkpoint is a substantial object to distribute and run, while about 3,200 CPU tokens per second on an L4 is not, by itself, evidence of competitiveness with ordinary execution. Teams should avoid converting a striking implementation claim into an infrastructure conclusion. The practical lesson is to demand workload-level comparisons before moving structured computation from conventional software into model inference.

## What happens next
- **The project will need a reproducible correctness or instruction-coverage evaluation to move beyond a demonstration claim.** (3 months, 65%). Watch for: a documented test suite or benchmark methodology.
- **Further projects will explore other executable structures compiled into Qwen-family checkpoints.** (6 months, 55%). Watch for: public checkpoints with source code and comparable measurements.

## Limits and uncertainty
The public source establishes that a Qwenputer checkpoint and a linked open-source code project have been published, alongside their stated size and one reported speed figure. It does not independently establish the mechanism of compilation, instruction-set coverage, correctness, memory model, supported workloads, or the meaning of “no external runtime” in a full deployment. There is no supplied benchmark protocol or comparison with hardware execution, software emulation, or related model-weight implementations. The performance claim should therefore be read as the project’s own reported measurement, not as a general capability result. No practical production use case is demonstrated in the supplied material.

## Skill to build now
Treat unusual model artifacts as systems to evaluate, not just checkpoints to sample. This week, make a small review template for any such project: identify the claimed execution boundary, record artifact size and hardware requirements, require a reproducible correctness test, and request a baseline on the same workload. That process is directly applicable here because the available record supplies a checkpoint size and one speed figure but not the test conditions needed to interpret them.

## Reader takeaway
Qwenputer claims to place a 32-bit RISC-V CPU inside Qwen3.5-4B’s weights, with public code and an 18.8 GB checkpoint. That is an interesting existence claim, not evidence that model-based CPUs are ready for production. The next meaningful evidence is reproducible correctness testing and a workload comparison against conventional execution.

## Open question
What instruction coverage and correctness evidence can Qwenputer provide, and how does its measured execution compare with a conventional RISC-V emulator on the same programs?

Editor: [Andrey Reshetnikov](https://newruntime.com/owner-profile.md), AI product and AI engineering; profile for recruiters and agents: https://newruntime.com/owner-profile.json

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